problem 2 Given A CMOS inverter 1 micron technology Kn 12mu

problem 2

Given: A CMOS inverter 1 micron technology K_n = (1/2)mu_n C_ox = 100 micro amp./sq. voltage K_p = (1/2)mu_P C_ox = 50 micro amp./sq. voltage C_L = 1 pF, Cg = 1 pF Logic-0 = 0.35 V_DD Logic-1 = 0.65 V_DD V_DD = 5V V_gamma =2.5 V Show the transistor level circuit and sketch the mask layout.(Use the attached grid layout) Estimate the Logical and the Silicon area of the CMOS In verier. (Use the attached grid layout) Derive the rise time and the fall time of the inverter. Calculate the propagation delay.

Solution

(a) Fan out of 5 means that 5 CMOS inverters are connected at the output of this inverter.

This means now load capacitance = CL + CG * 5 = 6pF, Based on this we can calculate the rise and fall time and propagation delay.

The answer will be 6 times the value calculated for question 1.

(b) suppose propagation delay is tpd. This measns it takes tpd time to propagate 1 bit.

or bit rate = 1/tpd.