Homework SourseWrite a VHDL code of digital safe lock 4 bits digit code and
Solution
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity digital_lock is
Port ( clk : in STD_LOGIC;
rst_bar : in STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC;
lock_pb_bar : in STD_LOGIC;
open_pb_bar : in STD_LOGIC;
door_closed_bar : in STD_LOGIC;
actuate_lock : out STD_LOGIC;
open_close : out STD_LOGIC;
seg_dig_0 : out STD_LOGIC_VECTOR (6 downto 0);
seg_dig_1 : out STD_LOGIC_VECTOR (6 downto 0));
end digital_lock;
architecture Behavioral of digital_lock is
component bcd_2dec
port (
clk : in STD_LOGIC;
cnt_en1_bar : in STD_LOGIC;
cnt_en2_bar : in STD_LOGIC;
rst_bar : in STD_LOGIC;
up_bar : in STD_LOGIC;
qbcd0 : out STD_LOGIC_VECTOR(3 downto 0);
qbcd1 : out STD_LOGIC_VECTOR(3 downto 0)
);
end component;
component bcd_7seg
port (
bi_bar : in STD_LOGIC;
dcba : in STD_LOGIC_VECTOR(3 downto 0);
lt_bar : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(6 downto 0)
);
end component;
component digit_compare
port (
bcd0 : in STD_LOGIC_VECTOR(3 downto 0);
bcd1 : in STD_LOGIC_VECTOR(3 downto 0);
num_sel : in STD_LOGIC_VECTOR(1 downto 0);
num_eq : out STD_LOGIC
);
end component;
component master_fsm
port (
clk : in STD_LOGIC;
cnt_en_bar : in STD_LOGIC;
dir_chngd : in STD_LOGIC;
door_closed_bar : in STD_LOGIC;
lock_pb_bar : in STD_LOGIC;
num_eq : in STD_LOGIC;
open_pb_bar : in STD_LOGIC;
rst_bar : in STD_LOGIC;
up_bar : in STD_LOGIC;
actuate_lock : out STD_LOGIC;
blank_bar : out STD_LOGIC;
clear_counters_bar : out STD_LOGIC;
cnt_en_bar_fsm : out STD_LOGIC;
num_sel : out STD_LOGIC_VECTOR(1 downto 0);
open_close : out STD_LOGIC
);
end component;
component ose_decoder_fsm
port (
a : in STD_LOGIC;
b : in STD_LOGIC;
clk : in STD_LOGIC;
rst_bar : in STD_LOGIC;
cten_bar : out STD_LOGIC;
dir_chngd : out STD_LOGIC;
up_bar : out STD_LOGIC
);
end component;
---- Constants -----
constant DANGLING_INPUT_CONSTANT : STD_LOGIC := \'Z\';
---- Signal declarations used on the diagram ----
signal DIR_CHNGD : STD_LOGIC;
signal BLANK_BAR : STD_LOGIC;
signal RST_BAR1 : STD_LOGIC;
signal CNT_EN2_BAR : STD_LOGIC;
signal CTEN_BAR : STD_LOGIC;
signal UP_BAR : STD_LOGIC;
signal QBCD1 : STD_LOGIC_VECTOR (3 downto 0);
signal NUM_SEL : STD_LOGIC_VECTOR (1 downto 0);
signal QBCD0 : STD_LOGIC_VECTOR (3 downto 0);
---- Declaration for Dangling input ----
signal Dangling_Input_Signal : STD_LOGIC;
begin
---- Component instantiations ----
U1 : ose_decoder_fsm
port map(
a => a,
b => b,
clk => clk,
cten_bar => CTEN_BAR,
dir_chngd => DIR_CHNGD,
rst_bar => rst_bar,
up_bar => UP_BAR
);
U2 : bcd_2dec
port map(
clk => Dangling_Input_Signal,
cnt_en1_bar => CTEN_BAR,
cnt_en2_bar => CNT_EN2_BAR,
qbcd0 => QBCD0,
qbcd1 => QBCD1,
rst_bar => RST_BAR1,
up_bar => UP_BAR
);
U3 : digit_compare
port map(
bcd0 => QBCD0,
bcd1 => QBCD1,
num_sel => NUM_SEL
);
U4 : master_fsm
port map(
actuate_lock => actuate_lock,
blank_bar => BLANK_BAR,
clear_counters_bar => RST_BAR1,
clk => clk,
cnt_en_bar => CTEN_BAR,
cnt_en_bar_fsm => CNT_EN2_BAR,
dir_chngd => DIR_CHNGD,
door_closed_bar => door_closed_bar,
lock_pb_bar => lock_pb_bar,
num_eq => Dangling_Input_Signal,
num_sel => NUM_SEL,
open_close => open_close,
open_pb_bar => open_pb_bar,
rst_bar => rst_bar,
up_bar => UP_BAR
);
U5 : bcd_7seg
port map(
bi_bar => BLANK_BAR,
dcba => QBCD0,
lt_bar => Dangling_Input_Signal,
seg => seg_dig_0
);
U6 : bcd_7seg
port map(
bi_bar => BLANK_BAR,
dcba => QBCD1,
lt_bar => Dangling_Input_Signal,
seg => seg_dig_1
);
---- Dangling input signal assignment ----
Dangling_Input_Signal <= DANGLING_INPUT_CONSTANT;
end Behavioral;
