Data out 14 O QQ Cir Cir Cir Cir D3 D2 Do CIN Load 1k Data

Data out 14 O QQ Cir Cir Cir Cir D3 D2 Do CIN Load- ( 1k Data in --!

Solution

for shift reg:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pipo is
Port ( ClrN,load,clk : in STD_LOGIC;
D3,D2,D1,D0 : in STD_LOGIC;
Q3,Q2,Q1,Q0 : out STD_LOGIC);
end pipo;

architecture Beh of pipo is
component D_ff is
Port ( clock,ClrN : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC);
end component;
signal clock:STD_LOGIC;
begin
clock<= load and clk;
u3:D_Ff port map(clock,ClrN,D3,Q3);
u2:D_Ff port map(clock,ClrN,D2,Q2);
u1:D_Ff port map(clock,ClrN,D1,Q1);
U0:D_Ff port map(clock,ClrN,D0,Q0);
end Beh

For DFF:

entity D_FF is
Port ( clock,ClrN : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC);
end D_FF;

architecture Behavioral of D_FF is

begin
process(clk,ClrN)
begin
if(ClrN = \'0\') then
if(falling_edge(clk)) then
Q <= D;
end if;
else
Q <= \'0\';
end if;
end process;

end Behavioral;