Input:A,B,C,D
Output:W,X,Y,Z
Below are the equations which represent the Braille printer.
W=B+C+A\'D+AD\'
X=A\'C\'D\'+BD\'+CD+AD
Y=(B+D\')(C\'+D)
Z=(A+B+D\')(B\'+C)
1. Write a Verilog HDL module describing the Braille printer. Use the same logic expressions (in terms of AND, OR, and NOT gates), same input and output names. Hint: you should have 4 assign statements
2. Write a VHDL module describing the Braille printer. Use the same logic expressions (in terms of AND, OR, and NOT gates), same input and output names.
Input:A,B,C,D
Output:W,X,Y,Z
Below are the equations which represent the Braille printer.
W=B+C+A\'D+AD\'
X=A\'C\'D\'+BD\'+CD+AD
Y=(B+D\')(C\'+D)
Z=(A+B+D\')(B\'+C)
1. Write a Verilog HDL module describing the Braille printer. Use the same logic expressions (in terms of AND, OR, and NOT gates), same input and output names. Hint: you should have 4 assign statements
2. Write a VHDL module describing the Braille printer. Use the same logic expressions (in terms of AND, OR, and NOT gates), same input and output names.
Input:A,B,C,D
Output:W,X,Y,Z
Below are the equations which represent the Braille printer.
W=B+C+A\'D+AD\'
X=A\'C\'D\'+BD\'+CD+AD
Y=(B+D\')(C\'+D)
Z=(A+B+D\')(B\'+C)
1. Write a Verilog HDL module describing the Braille printer. Use the same logic expressions (in terms of AND, OR, and NOT gates), same input and output names. Hint: you should have 4 assign statements
2. Write a VHDL module describing the Braille printer. Use the same logic expressions (in terms of AND, OR, and NOT gates), same input and output names.
//1)Verilog Code
module braille(a,b,c,d,w,x,y,z);
//Input Decleration
input [7:0] a;
input [7:0] b;
input [7:0] c;
input [7:0] d;
//Output Decleration
output w;
output x;
output y;
output z;
reg w;
reg x;
reg y;
reg z;
//register to store intermediate values.16 bit as output may exceed 8 bit
reg [16:0] t1;
reg [16:0] t2;
reg [16:0] t3;
reg [16:0] t4;
reg [16:0] t5;
reg [16:0] t6;
reg [16:0] t7;
reg [16:0] t8;
reg [16:0] t9;
reg [16:0] t10;
always@(a or b or c or d) //always at at least one input
begin
t1 = a & (~d);
t2 = (~a) & (d);
t3 = ((~a) & (~c))&(~d);
t4 = b & (~d);
t5 = C & d;
t6 = a & d;
t7 = b | (~d);
t8 = (~c) | d;
t9 = a | b | (~d);
t10 = (~b) | c;
//output calculation
w = b | c | t1 | t2;
x = t3 | t4 | t5 | t6;
y = t7 & t8;
z = t9 & t10;
end
endmodule
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