The timing parameters of the components used in the followin

The timing parameters of the components used in the following circuit are given as follows. Answer questions based on these data. In your answer, you have to write down the equations that you use. You CANNOT just write a number as your solution. Calculate the maximum external setup time. Calculate the maximum external hold time. Calculate the maximum clock to output delay. If the clock frequency is 500MHz and the propagation delay of the OR gate changes to 0.6ns. what type of timing violation will occur in the circuit? Why? If the propagation delay of the OR gate changes to 0.2 ns. what type of timing violation will occur in the circuit? Why? Assume there exist clock skew due to interconnect delay. Clk1 is 0.1ns earlier than clk2. Clk2 is 0.1ns earlier than clk3. Considering clock skew, what type of timing violation will occur in the circuit? Why? How to fix the timing violation problem discussed in the previous question? After the problem is fixed, what\'s the maximum clock frequency of the new circuit?

Solution

1.1) tpdff(clk-q) + tpd(or) + tdff su = 0.5 ns + 0.4 ns + 0.5 ns = 1.4 ns

Tw max = tpdff (clk-q) + tpdxor + tpd or + tdffsu = 0.5 ns +0.6 ns + 0.4 ns + 0.5 ns = 2 .0 ns = 500 mhz