Design a 4bit 2s complement format addersubtractor circuit t

Design a 4-bit 2’s complement format adder/subtractor circuit that is also capable of indicating the occurrence of an overflow condition. The circuit has two 4-bit inputs, P and S, and a 1-bit input Op. The value of Op specifies whether the operation to be carried out is addition or subtraction. The outputs for the circuit are R (4-bit wide) and Ov (1-bit wide; Ov =1 indicates the occurrence of an overflow during the addition/subtraction process and Ov = 0 indicates that there is no overflow).

Write a short report.

The report should contain the following:

1. A Problem statement or Objective statement

2. A Methodology section. In this section, you need to discuss your design approach.

3. A Discussion section. In this section, you need to discuss your results. You must also discuss any difficulties that you faced while working on this assignment and how you overcame them. In addition, you should also indicate what you learned after finishing this assignment.

4. Snapshots of the results for the 8 cases that you have been asked to verify

(four cases of P + S and four cases of P – S as specified above)

5. Your conclusions

Solution

C 4-bit lookahead unit G1 P1 G0 P0 G P C0 C1 C2 G2 P2 C 4-bit adder (a) (b) A S G P C4 B

Product Term Inputs Outputs Number Function 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 1 ••••• 1 2 ••••• 1 3 ••••• 1 4 ••••• 1 5 •••• 1 • 6 •••• 1 • 7 x1x2\'x5x7x11\'x12 1 0 – – 1 – 1 ––– 0 1 ••• 1 • • 8 ••• 1 • • 9 • • 1 ••• 10 • • 1 ••• 11 • 1 •••• 12 • 1 •••• 13 1 ••••• 14 1 ••••• 15 1 ••••• 16 1 •••••

links at the outputs. For the example in Figure 23, the number of links is 4(6 + 4) = 40. Only 16 of these are to be kept, meaning that, during field programming, 24 links are to be blown out. Typical PLAs have many more inputs, outputs, and AND gates than are shown in the example in Figure 23. (IC type 82S100, for example, has n = 16, m = 8, and p = 48.) When a set of switching functions is presented for implementation with a PLA, a design goal would be reduction in p (the number of AND gates). The economy achieved is not derived from a reduction in the production cost of gates. (The production cost of an IC is practically the same for one with 40 gates as it is for one with 50 gates.) Rather, the removal of one AND gate eliminates 2n + m links; the main source of savings is the elimination of a substantial number of links due to the elimination of each AND gate. On the other hand, reduction of the number of AND gates to a minimum does not mean that each function should be minimized or that all implicants should be prime implicants. The implicants should be chosen so that as many as possible of them are common to many of the output functions.