Code the input stimulus pattern below for a Verilog simulati

Code the input stimulus pattern below for a Verilog simulation. Note that all input transitions are in increments of 10 time units. So the input B changes from a logic 1 to a logic 0 at time 40 time units.

Solution

The sequence are

at iniital-010,

#10-011,

#20-111,

#30-110,

#40-101,

#50-010,

#60-010,#70-101,#80-101

module stimu

reg A,B,C;

initial

begin

A=0;B=1;C=0;

#10 A=0;B=1;C=1;

#10 A=1;A=1;A=1;

#10 A=1;B=1;C=0;

#10 A=1;B=0;C=1;

#10 A=0;B=1;C=0;

#10 A=0;B=1;C=0;

#10 A=1;B=0;C=1;

#10 A=1;B=0;C=1;

#10 A=1;B=0;C=1;

$finish;

end

endmodule