CSC201 Assignment A1 50 pts Write an assembler program that

CSC201 Assignment A1 (50 pts) Write an assembler program that displays a certificate exactly like the one below: ***kkXE This Certifies that Iman A. Student has mastered Input/Output * in Assembly Language Grade: Today\'s date: mm/dd/yyyy where: . there are 30 asterisks across (with spaces in between), 5 on sides the columns of asterisks on each side are aligned text is centered * there are no literals in the code (i.e. no literal*, in·CODE.) o use only named symbolic constants or variables (in .DATA.) o It should be hard-coded in .DATA, don\'t get it from the user o use exactly the following prompt: Instead of Iman A. Student, display your name Prompt the user for the letter grade (a character) Please enter the letter grade o Instead of? on the Grade line, display the letter the user entered . Retrieve the system date using a macro o Display the system date instead of mm/dd/yyyy in this exact format .all other data should be hard-coded in .DATA (not entered by user) the program uses macros and calls functions whenever possible o use only macros and functions shown in Chapter 3 You must use the macros in Chapter 3 instead of assembler code previously used.use only code that is covered in Chapters 1-3 (i.e. no jumps/loops or branching/if statements!) Extra Credit on the next page!

Solution

What these FPGAs do have, rather than FPUs, is hardwired DSP/multiplier squares, equipped for actualizing a 18*18 or (Virtex-5) 18*25 duplication in a solitary cycle. Furthermore, the bigger gadgets have around a thousand of these, or even 126 or 180 at the top end of the Spartan-3 or Spartan-6 families.

So you can decay a huge augmentation into littler operations utilizing a few of these (2 for the Virtex-5 doing single exactness) utilizing the DSP\'s adders or FPGA texture to whole the fractional items.

You will get a reply in a couple cycles - 3 or 4 for SP, possibly 5 for DP - relying upon how you form the viper tree (and some of the time, where the synth apparatuses demand including pipeline registers!).

However that is the dormancy - as it is pipelined, throughput will be 1 result for each clock cycle.

For division, I approximated a proportional administrator utilizing a query table took after by quadratic interjection. This was exact to superior to anything single-exactness and would stretch out (with more equipment) to DP on the off chance that I needed. In Spartan-6 it takes 2 BlockRams and 4 DSP/multipliers, and several hundred LUT/FF sets.

Its inertness is 8 cycles, however again the throughput is single-cycle, so by joining it with the above multiplier, you get one division for every clock cycle. It ought to surpass 100MHz in Spartan-3. In Spartan-6 the amalgamation gauge is 185MHz yet that is with 1.6ns on a solitary directing way, so 200MHz is inside reason.

In Virtex-5 it achieved 200MHz without exertion, as did its square root twin. I had two or three summer understudies endeavor to re-pipeline it - with under 12 cycles dormancy they drew near to 400MHz - 2.5 ns for a square root.

Be that as it may, recall that you have perhaps a hundred to a thousand DSP units? That gives you maybe a couple requests of extent more preparing force than a solitary FP unit.