Using VHDL code Modify your existing JK flip flop to include

Using VHDL code

Modify your existing JK flip flop to include a reset signal. Use the following diagram to design a binary counter that counts from 15 to 0, back to 15. Include a main reset signal for the binary counter. Note that the JK flip-flops are tied to logic \'1\'. Explain why?

Solution

VHDl code:

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:59:54 10/15/2016
-- Design Name:
-- Module Name: downcounter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity downcounter is
Port ( clk : in std_logic;
reset : in std_logic;
count : out std_logic_vector(3 downto 0)
);
end downcounter;

architecture Behavioral of downcounter is
COMPONENT jkff
PORT(
clock : in std_logic;
clear : in std_logic;
j : in std_logic;
k : in std_logic;
q : out std_logic
);
END COMPONENT;
signal temp : std_logic_vector(3 downto 0) := \"1111\";
begin
d0 : jkff
port map (
clear => reset,
clock => clk,
j => \'1\',
k => \'1\',
q => temp(0)
);

d1 : jkff
port map (
clear => reset,
clock => temp(0),
j => \'1\',
k => \'1\',
q => temp(1)
);

d2 : jkff
port map (
clear => reset,
clock => temp(1),
j => \'1\',
k => \'1\',
q => temp(2)
);

d3 : jkff
port map (
clear => reset,
clock => temp(2),
j => \'1\',
k => \'1\',
q => temp(3)
);
count(0) <= temp(0);
count(1) <= temp(1);
count(2) <= temp(2);
count(3) <= temp(3);   
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
entity jkff is
Port( clock : in std_logic;
clear : in std_logic;
j : in std_logic;
k : in std_logic;
q : out std_logic );
end jkff;

architecture rtl of jkff is
signal jk : std_logic_vector(1 downto 0) := \"00\";
signal qsig : std_logic := \'0\';
  
begin
jk <= j & k;
process(clear,clock)
begin
if (clear = \'0\')then
qsig <=\'1\';
elsif (clock\'event and clock = \'1\')then
case (jk) is
when \"00\" => qsig <= qsig;
when \"01\" => qsig <= \'0\';
when \"10\" => qsig <= \'1\';
when others => qsig <= not qsig;
end case;
end if;
end process;
  
q <= qsig;
end rtl;

when JK both tied to gether and apply1 , the flip flop in Toggle condition whic is the base reuriement of counter