Design a block diagram in RTL an 8bit Data Processing Unit w

Design a block diagram in RTL an 8-bit Data Processing Unit with the following specifications and requirements:
1- The ALU is capable of executing the following functions:
a- load, store, shift-left, and shift-right
b- add, add-with-carry, sub, increment
c- and, or, xor, and complement
d- set-a-flag, clear-a-flag, test-a-flag
e- branch-if-zero, and branch-if-carry
2- Use a file register ALU architecture organization for yourdesign.3- Include the following flags in your design: C, Z, V, &N.
4- Include documentation describing your design at the register level
(RTL), which should include the following:
a- Hardware design for the data processing unit (which
includes the bus system) that is capable of executing the required functions
b- A block diagram for your processor architecture
c- State all the control signals that are needed for your
design (you have to justification your choices)

Solution

use ieee.std_logic_unsigned.all;

entity alu is
   port(
       din1 : in STD_LOGIC_VECTOR(3 downto 0);
       din2 : in STD_LOGIC_VECTOR(3 downto 0);
       sel : in STD_LOGIC_VECTOR(3 downto 0);
       dout : out STD_LOGIC_VECTOR(3 downto 0)
   );
end alu;

architecture alu_arc of alu is     

begin
   with sel select  
   dout <= din1 and din2 when \"0000\",
           din1 or din2 when \"0001\",
           din1 nand din2 when \"0010\",
           din1 nor din2 when \"0011\",
           din1 xor din2 when \"0100\",
           din1 xnor din2 when \"0101\",
           not din1 when \"0110\",
           not din2 when \"0111\",
             
           din1 + \"0001\" when \"1000\",
           din2 + \"0001\" when \"1001\",
           din1 + din2 when \"1010\",
           din1 - din2 when \"1011\",
           din2 - \"0010\" when \"1100\",
           din1 - \"0010\" when \"1101\",
           din1 + \"0010\" when \"1110\",
           din2 + \"0010\" when others;
         
end alu_arc;