Using two 4bit registers with parallel load here they are re

Using two 4-bit registers with parallel load (here they are referred as RI and R2) four 2xl multiplexers, and five inverters, draw the block diagram of the circuit that implements the following operations: ion X 0 clear R2 0 complement the content of R2 l transfer the content from R1 to R2 1 where S and E are the control inputs. The block diagrams of the registers (and multiplexers are shown below select L/P select data0 UP 4-bit register 2x1 F MUX O/P clk D CBA load clr where clr and load are synchronous active-low inputs ie., when the rising edge of the clock arrives at the clk input, the one of the following operations will be performed clr load ons X clear 0 parallel load 1 no change

Solution

For the block diagram with the description provided, the beahviour of the 4 bit register with clr and load inputs is clearly understood. clr and load are synchronous active-low inputs.

Case 1) When the input E turns 0 the clr signal sets zero and the the 4 bit register R2\'s content is cleared.

Case 2) Now the input E is observed to be 1. This indicates the working of 4 bit register without clearing the content. Due the presence of inverter for load, this would be set 1. The S is observed to be 0 and feeds each of the multiplexers with the same 0. Thus complementing the R2 through the output of each multiplexer.

Case 3) Now as the load is enabled and the clr is not set 0. We observe the S to be 1 thus transferring of data from R1 to R2, through the path QD (R1) to Multiplexer to R2, Each multiplexer follows the same, finally transferring the content from R1 to R2.