Calculate the unit delays for an Inverter twoinput NOR and t

Calculate the unit delays for an Inverter, two-input NOR, and two-input NAND in 0.18u CMOS. Assume pull down by a 1u NMOS, or eqiuivalent and matched pull up.

Solution

The normalised delay of an Inverter can be calculated as
d = gh + p
and the logical effort for 2 input NAND gate g = 4/3 and that for NOR g = 5/3
Putting this in the above equations,
d = (4/3) (1) + 2 = 10/3 for NAND
d = (5/3) (2) + 1 = 13/3 for NOR