Type and show the complete Verilog code for a One Digit BCD

Type and show the complete Verilog code for a \"One Digit BCD Decoder\". The truth table of this decoder is given below. You should download this *.doc file and type your code below the truth table. Show two version of the code: Use the Verilog IF ELSE statement covered in module 16. Use the Verilog CASE statement covered in module 16.

Solution

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:41:29 11/02/2016
// Design Name:
// Module Name: BCD_Decoder
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module BCD_Decoder(
input [3:0] B,
output reg [9:0] D
);
always@(B)
begin
if(B==4\'d0)
begin
D=10\'b0000000001;
end
else if(B==4\'d1)
begin
D=10\'b0000000010;
end
else if(B==4\'d2)
begin
D=10\'b0000000100;
end
else if(B==4\'d3)
begin
D=10\'b0000001000;
end
else if(B==4\'d4)
begin
D=10\'b0000010000;
end
else if(B==4\'d5)
begin
D=10\'b0000100000;
end
else if(B==4\'d6)
begin
D=10\'b0001000000;
end
else if(B==4\'d7)
begin
D=10\'b0010000000;
end
else if(B==4\'d8)
begin
D=10\'b0100000000;
end
else if(B==4\'d9)
begin
D=10\'b1000000000;
end
else
begin
D=10\'b0000000000;
end;
end;

endmodule

Using case statement:

module BCD_Decoder(
input [3:0] B,
output reg [9:0] D
);
always@(B)
case(B)
0:D=10\'b0000000001;
1:D=10\'b0000000010;
2:D=10\'b0000000100;
3:D=10\'b0000001000;
4:D=10\'b0000010000;
5:D=10\'b0000100000;
6:D=10\'b0001000000;
7:D=10\'b0010000000;
8:D=10\'b0100000000;
9:D=10\'b1000000000;
default:D=10\'b0000000000;
endcase

endmodule