Using the state diagram shown below briefly explain the oper

Using the state diagram shown below, briefly explain the operation of the circuit shown. Create the VHDL text file for the state machine described in Problem 3. Using the state diagram shown below, how many state variables are required to implement this state machine? Why? Create the VHDL text file for the state machine described in Problem 6.

Solution

3)

In this state diagram,There are four states S0,S1,S2,S3 .

First let us be in state S3,

Present state:S3 & input X :any of 0/1 =>It will move to state S0    => Next state :S0 & Output O1/O2 :0/0

After this ,

Present state:S0 & input X :1 =>It will move to state S0    => Next state :S0 & Output O1/O2 :0/0

Present state:S0 & input X :0 =>It will move to state S1    => Next state :S1 & Output O1/O2 :1/0

After it,

Present state:S1 & input X :0 =>It will move to state S1    => Next state :S1 & Output O1/O2 :0/0

Present state:S1 & input X :1 =>It will move to state S2    => Next state :S2 & Output O1/O2 :0/1

After this,

Present state:S2 & input X :any value 0/1 =>It will move to state S0    => Next state :S0 & Output O1/O2 :0/0

We observe that

output O1 goes high when input has 0 when it is in S0 state.

output O2 goes high when input 01 is in the sequence.

4)

library ieee;
use IEEE.std_logic_1164.all;

entity stateMac is
port (clk : in std_logic;
      reset : in std_logic;
      input : in std_logic;
      output   : OUT STD_LOGIC_VECTOR(1 downto 0));
);
end stateMac;

architecture behavioral of stateMac is

type state_type is (s0,s1,s2,s3);     --type of state machine.
signal present_s,next_s: state_type; --current and next state declaration.

begin

process (clk,reset)
begin
if (reset=\'1\') then
present_s <= s3; --default state on reset.
elsif (rising_edge(clk)) then
present_s <= next_s;   --state change.
end if;
end process;

--state machine process.
process (present_s,input)
begin
case present_s is
     when s0 =>        --when current state is \"s0\"
     if(input =\'0\') then
      output <= \'10\';
      next_s <= s1;
    else
      output <= \'00\';
      next_s <= s0;
     end if;

     when s1 =>;        --when current state is \"s1\"
    if(input =\'0\') then
      output <= \'00\';
      next_s <= s1;
    else
      output <= \'01\';
      next_s <= s2;
    end if;

    when s2 =>       --when current state is \"s2\"
    if(input =\'0\') then
      output <= \'00\';
      next_s <= s1;
    else
      output <= \'00\';
      next_s <= s1;
    end if;

when s3 =>         --when current state is \"s3\"
    if(input =\'0\') then
      output <= \'00\';
      next_s <= s0;
    else
      output <= \'00\';
      next_s <= s0;
    end if;
end case;
end process;

end behavioral;

6)

As there are total 5 states to implement.So we can use 3 state variables for it as with three variables we can have maximum state of 2³=8 states.

7)

library ieee;
use IEEE.std_logic_1164.all;

entity stateMac is
port (clk : in std_logic;
      reset : in std_logic;
      input : in std_logic;
      output   : OUT STD_LOGIC_VECTOR(1 downto 0));
);
end stateMac;

architecture behavioral of stateMac is

type state_type is (s0,s1,s2,s3,s4);     --type of state machine.
signal present_s,next_s: state_type; --current and next state declaration.

begin

process (clk,reset)
begin
if (reset=\'1\') then
present_s <= s3; --default state on reset.
elsif (rising_edge(clk)) then
present_s <= next_s;   --state change.
end if;
end process;

--state machine process.
process (present_s,input)
begin
case present_s is
     when s0 =>        --when current state is \"s0\"
     if(input =\'0\') then
      output <= \'-0\'; -- \"-\" used for don\'t care
      next_s <= s1;
    else
      output <= \'-0\';
      next_s <= s1;
     end if;

     when s1 =>;        --when current state is \"s1\"
    if(input =\'0\') then
      output <= \'x0\';
      next_s <= s2;
    else
      output <= \'-0\';
      next_s <= s1;
    end if;

    when s2 =>       --when current state is \"s2\"
    if(input =\'0\') then
      output <= \'-0\';
      next_s <= s3;
    else
      output <= \'-0\';
      next_s <= s3;
    end if;

when s3 =>         --when current state is \"s3\"
    if(input =\'0\') then
      output <= \'-0\';
      next_s <= s4;
    else
      output <= \'-0\';
      next_s <= s4;
    end if;

when s4 =>         --when current state is \"s3\"
    if(input =\'0\') then
      output <= \'01\';
      next_s <= s0;
    else
      output <= \'01\';
      next_s <= s0;
    end if;
end case;
end process;

end behavioral;