Write VHDL code for a modulo13 counter counting sequence is

Write VHDL code for a modulo-13 counter (counting sequence is 0_10, 1_10, TripleDot 12_10). The counter has the following features: bullet an asynchronous active Low Reset bullet a value R can be loaded into the counter, using the signal Ld (Load) The signal Ld is active Low. Draw the schematic of your counter, showing the inputs and outputs Show the number of bits for R, Q (output of the counter), Ld.

Solution

VHDL Code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port(Clk,rst, Ld : in std_logic;
R : in std_logic_vector(3 downto 0);
Q : out std_logic_vector(3 downto 0));
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (clk,rst, Ld, R)
begin
if (rst=\'0\') then
tmp <= \"0000\";
elsif (Ld=\'0\') then
tmp <= R;
elsif (clk\'event and Clk=\'1\') then
tmp <= tmp + 1;
end if;

end process;
Q <= tmp;
end archi;