For the following VHDL segment correct the type mismatch wit

For the following VHDL segment, correct the type mismatch with proper conversion function

For the following VHDL segment, correct the type mismatch with proper conversion function(s). library ieee; use ieee. std_logic_1164. all; use ieee. std_logic_arith. all; use ieee. std_logic_unsigned. a ll;. .. signal src, dest: std_logic_vector(15 downto 0); signal amount: std_logic_vector(3 downto 0);. .. dest

Solution

amount of shift must be a decimal number. so need not to define it. it should be sepecified in the assignment statement itself.

here given amount (3 down to 0). the maxmium count is (1111)₂=(15)₁₀

_so the code can be modified as

signal src,dest:std_logic_vector(15 down to 0);

dest <= src sll 15;