A binary adder is simply a series of logic gates that mimic

A binary adder is simply a series of logic gates that mimic the algorithm we have used for addition. In fact, there are a number of ways to design a binary adder. Here we will describe one in digital functions. Your task is to use Logisim to implement the adder and test it. Full Adder Logic Function: Sum_i = A_i Carry_out = A_i middot B_i + middot C_in I am showing you a single bit of the adder. You need to create an adder capable of computing 4 bits at a time. A0 + B0 produces a sum bit and a carry bit. The carry bit (Carry_out) then moves to the next column and becomes part of that addition. First build a single bit version using the exact functions above, then replicate those circuits to add 2 4-bit numbers. A_3A^2A_1A_0 + B_3 B_2 B_1 B_0 = S_3S_2S_1S_0 As we have seen, transistors have a resistive and capacitive component, resulting in a time delay of the transistor. Given that, why would this adder be slow? What if I make it 32 bits or more? To what did you set the original carry in? Why? What do you do with the last carry out? Why? Does this hardware work if my inputs are in 2\'s complement format? Why or why not? Does this hardware work if my inputs are in unsigned format? Why or why not?

Solution

1. As every gate is designed with transistors, diodes, capacitors will result the propagation delay. i.e the output of the gate will take certain to change its state after input changes. If the bit size increased that will rise the delay as here the present carry will be generated after previous 2 bits addition.

2. The original carry in is set to 0. Because the carry will be generated only after one addition.

3. The last carry out will be neglected that is called over flow. As we need fixed number of bits addition or subtraction.

4. Yes. It can be used for 2s compliment. As the range of numbers in the 2s compliment form are changed.

5. Yes, If it is unsigned format the final carry out will represent the most significant bit of the result