Draft the behavioral verilog module for the FSM Hint You may

Solution

`timescale 1ns/1ns

module fsm1 (
clock,reset,X,
Y[1:0]);

input clock;
input reset;
input X;
tri0 reset;
tri0 X;
output [1:0] Y;
reg [1:0] Y;
reg [5:0] fstate;
reg [5:0] reg_fstate;
parameter S0=0,S1=1,S2=2,S3=3,S4=4,S5=5;

always @(posedge clock)
begin
if (clock) begin
fstate <= reg_fstate;
end
end

always @(fstate or reset or X)
begin
if (~reset) begin
reg_fstate <= S0;
Y <= 2\'b00;
end
else begin
Y <= 2\'b00;
case (fstate)
S0: begin
reg_fstate <= S1;

if (~(X))
Y <= 2\'b00;
else if (X)
Y <= 2\'b10;
// Inserting \'else\' block to prevent latch inference
else
Y <= 2\'b00;
end
S1: begin
if (~(X))
reg_fstate <= S2;
else if (X)
reg_fstate <= S4;
// Inserting \'else\' block to prevent latch inference
else
reg_fstate <= S1;

if (~(X))
Y <= 2\'b10;
else if (X)
Y <= 2\'b00;
// Inserting \'else\' block to prevent latch inference
else
Y <= 2\'b00;
end
S2: begin
reg_fstate <= S3;

if (~(X))
Y <= 2\'b00;
else if (X)
Y <= 2\'b10;
// Inserting \'else\' block to prevent latch inference
else
Y <= 2\'b00;
end
S3: begin
reg_fstate <= S0;

if (~(X))
Y <= 2\'b00;
else if (X)
Y <= 2\'b10;
// Inserting \'else\' block to prevent latch inference
else
Y <= 2\'b00;
end
S4: begin
if (~(X))
reg_fstate <= S3;
else if (X)
reg_fstate <= S5;
// Inserting \'else\' block to prevent latch inference
else
reg_fstate <= S4;

if (~(X))
Y <= 2\'b10;
else if (X)
Y <= 2\'b00;
// Inserting \'else\' block to prevent latch inference
else
Y <= 2\'b00;
end
S5: begin
reg_fstate <= S0;

if (~(X))
Y <= 2\'b10;
else if (X)
Y <= 2\'b01;
// Inserting \'else\' block to prevent latch inference
else
Y <= 2\'b00;
end
default: begin
Y <= 2\'bxx;
$display (\"Reach undefined state\");
end
endcase
end
end
endmodule // fsm1