Use Verilog to design a 4 bit Comparator Circuit using hiera

Use Verilog to design a 4 bit Comparator Circuit using hierarchical design techniques as discussed in the class. Your design will have two inputs A and B, each with 4 bits. 4 bits will make it possible for the inputs to have values from 0000 to 1111 in binary or 0 to F in hexadecimal. You are provided a Test Bench for your 4 bit Comparator, which is shown below. You will need to specify the values for A and B (in HEX) exactly as shown.

Solution

module comparator4bit(
input [3:0] A,B,
output Gt,Eq,Lt
);
wire e3,e2,e1,e0,g3,g2,g1,g0,l3,l2,l1,l0;
comparator_1bit c3(A[3],B[3],g3,e3,l3);
comparator_1bit c2(A[2],B[2],g2,e2,l2);
comparator_1bit c1(A[1],B[1],g1,e1,l1);
comparator_1bit c0(A[0],B[0],g0,e0,l0);
assign Gt=g3|(e3 & g2)|(e3 & e2 & g1)|(e3 & e2 & e1 & g0);
assign Eq= (e3 & e2 & e1 & e0);
assign Lt=l3|(e3 & l2)|(e3 & e2 & l1)|(e3 & e2 & e1 & l0);
endmodule

module comparator_1bit(
input A,B,
output gt,eq,lt
);

assign gt=A & (~B);
assign eq=A ~^ B;
assign lt=(~A) & B;

endmodule