What is branch target address What is pipelining of a comput

What is branch target address? What is pipelining of a computer processor? And what is pipeline hazard? What is pipeline data hazard? And what is load-use data hazard? What is Temporal locality? And what is Spatial locality? What is hit time? And what is miss penalty?

Solution

1. In computer architecture, a branch target predictor is the branch of a processor that forecasts the target of an in use conditional branch or an unqualified branch instruction previous to the target of the branch instruction is calculated by the execution unit of the processor. Instruction gets restarts at branch target.

2. Instruction pipelining is a method that implements a form of parallelism named instruction level parallelism inside a solitary processor. It so allows faster CPU throughput than would or else be probable at a given clock rate

A pipeline hazard submits to a situation in which a correct program finishes to work correctly due to executing the processor with a pipeline. Present are three fundamental kinds of hazard: data hazards, branch hazards, and structural hazards.