Write VHDL code to describe the absolute value circuit from

Write VHDL code to describe the absolute value circuit from Exercise 4, using k = 8 bits. The VHDL module should be called Problem4, it should accept two 8-bit inputs called A and B. and produce one 8-bit output Y which is the absolute value of A + B. Your solution should include both a schematic and the corresponding VHDL code. You can access the most significant bit of an 8-bit signal S by writing S(7).

Solution

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Problem4 is
Port ( A : in signed (7 downto 0);
B : in signed (7 downto 0);
Y : out signed (7 downto 0));
end Problem4;

architecture Behavioral of Problem4 is
signal x:signed (8 downto 0);
begin
process(A,B)
begin
x<=A+B;
Y<=x(7 downto 0);
end process;
end Behavioral;