The whenelse conditional signal assignment offers an alterna

The \"when/else\" conditional signal assignment offers an alternative to the IF statement. Unlike Case, with/select does not go in a process, so it is quicker to write. Being outside the process it must be kept simple (no nesting for example). The code below makes Z = \"101\" when ADDR = \"01\" or \"10\", Z = \"111\" when ADDR = \"11\" and Z = \"000\" for all other ADDR values (ADDR = \"00\"). Rewrite the VHDL code replacing the \"with/select\" with a Case statement. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity hwl2_p3 is Port (signal ADDR: in STD_LOGIC_VECTOR(1 DOWNTO 0); signal Z out: STD_LOGIC_VECTOR(2 DOWNTO 0)); end hw12_p3; architecture behavioral of hw12_p3 is begin outside all processes Z

Solution

entity hw_12p1 is
Port ( ADDR : in STD_LOGIC_VECTOR (1 downto 0);
Z : out STD_LOGIC_VECTOR (2 downto 0));
end hw_12p1;

architecture Behavioral of hw_12p1 is

begin
process(ADDR)
begin
case ADDR is
when \"00\"=>Z<=\"000\";
when \"01\"=>z<=\"101\";
when \"10\"=>Z<=\"101\";
when \"11\"=>z<=\"111\";
end case;
end process
end Behavioral;