LIBRARY ieee USE ieeestdlogic1164ALL ENTITY count is PORTcp

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY count is PORT(cp, n_rd, n_pl, n_ce, u_d:In std logic.; pl data IN integer RANGE 0 to 15; q BUFFER integer RANGE integer Range 0 TO 15); END count; ARCHITECTURE arc OF count IS BEGIN PROCESS (cp, n, rd, n pl) BEGIN IF (n rd=0 AND n pl = 1) THEN q

Solution

a)n_rd,n_pl are asynchronus i/p

b)n_ce is used to hold the curretn counter value.

e) n_rd=1 and n_pl=1 the module enter to syn mode, when cp=1 its hold the current counting value so q=9