Write VHDL code for traffic light design for quartus II incl

Write VHDL code for traffic light design for quartus II, include kanaugh map. and timers in the code.

Solution

The traffic light controller must handle a four-phase signal intersection. If we consider only straight way direction when NS street is on then traffic is followed by North to South or South to North alternatively. During this EW street traffic is stopped by Red signal. After completion of NS street now EW street traffic is followed by East to West or West to East alternatively. If we considered another

possibility to follow traffic in another direction rather than straightway direction, we can see from figure that during NS street on vehicles can go to left or right direction according to North-South direction parallelly to main direction because EW street is OFF during this. Similarly we can say about EW Street.

Problem Statement: A traffic light at the intersection of north-south(NS) and east-west(EW)

-- streets goes through the following cycles of states : both red(5 sec), NS green (30 sec), NS yellow(5 s)

-- both red(5s) EW green(30 sec) EW yellow (5sec).

-- A 0.2 Hz clock signal is available for timing. Both streets are equipped with sensors that detects the presence of a car close to the intersection.Whenever there is a car close to the intersection on the street currently having its light red while there is no car approaching the intersection on the street with green light, the switchover takes place and green light immediately turns to yellow.

Traffic light controller(TLC)

CODE:-

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity tlc_project is

port(t,clk,sensor1,sensor2:in std_logic;

          presetn :in std_logic;

            enable: out STD_LOGIC_VECTOR(3 downto 0);

            seg7 : out STD_LOGIC_VECTOR(6 downto 0);

          g1,y1,r1,g2,y2,r2: buffer std_logic

);

end entity;

-- architecture declaration

architecture trafficlightcontroller of tlc_project is

signal count : std_logic_vector(3 downto 0);

signal a,b,c,d:std_logic;

signal temp:std_logic_vector(2 downto 0);

begin

counter:process(clk,t,presetn) is

begin

if(t=\'0\')then

  enable <= \"0111\";

  seg7 <= \"0110000\";   

  elsif(presetn = \'0\') then

  count <= \"1111\";   

  elsif((clk=\'1\' and clk\'event) and (t=\'1\')) then     

  count <= count + 1;

a<= count(3);

b<= count(2);

c<= count(1);

d <= count(0);

  r1 <= (((not b)and (not c) and (not d)) or (a));

  r2 <= (((not b)and (not c) and (not d)) or (not a));   

  g1 <= (((b and (not c)) or ((not b) and d) or (c and (not d))) and (not a));

  g2 <= (((b and (not c)) or ((not b) and d) or (c and (not d))) and (a));

  y1 <= (b and c and d and (not a));

  y2 <= (b and c and d and (a));   

    if ((g1=\'1\' and sensor1=\'0\') or (g2=\'1\' and sensor2=\'0\')) then

   count(2 downto 0) <= \"111\";

b<=\'1\';

c<=\'1\';

d<=\'1\';

end if;

  temp <= b&c&d;   

  case temp is

   when \"000\" => seg7 <= \"0000001\";

   when \"001\" => seg7 <= \"1001111\";

   when \"010\" => seg7 <= \"0010010\";

   when \"011\" => seg7 <= \"0000110\";

   when \"100\" => seg7 <= \"1001100\";

   when \"101\" => seg7 <= \"0100100\";

   when \"110\" => seg7 <= \"1100000\";

   when \"111\" => seg7 <= \"0001111\";

   when others => seg7 <= \"1111110\";

    end case;

  case temp is

     when \"000\" => enable <= \"0111\";

     when \"001\" => enable <= \"1011\";

     when \"010\" => enable <= \"1101\";

     when \"011\" => enable <= \"1110\";

     when \"100\" => enable <= \"0111\";

when \"101\" => enable <= \"1011\";

     when \"110\" => enable <= \"1101\";

     when \"111\" => enable <= \"1110\";

     when others => enable <= \"0111\";

end case;

end if;  

end process;

end architecture;