Write Verilog code for a Mealytype FSM implementing a BCD to

Write Verilog code for a Mealy-type FSM implementing a BCD to Excess-3 code converter. Using figure 3.22

Figure 3.22 Circuit for a Mealy-type FSM implementing a BCD to Excess-3 code converter D Q q1 qo reset D Q q1 in q2 q1 D Q in 92 in q1 clk out

The code is as folloes as:

Module BCD_to_Excess_3b_V2001(output reg B_out, input B_in, clk,reset_b); //state assignment are non blocking parameters

S_1=3’b001,

S_1=3’b101,

S_1=3’b111,

S_1=3’b011,

S_1=3’b110,

S_1=3’b010,

Don’t_care_state=3’bx,

Don’t_care _out=1’bx;

Reg [2:0] state,next_state;

always@ (posedge clk, negative reset_b)

if (reset_b==0 state<=S_0;else state<=next_state;

always @(state, B_in) begin

B_out=0;

Case(state)

S_0:if(B_in==0) begin next _state =S_1;B_out=1; end

Else if(B_in==1) begin next_state=S_2;end

S_1:if(B_in==0) begin next _state =S_3;B_out=1; end

Else if(B_in==1) begin next_state=S_4;end

S_2:begin next_state=S_4;B_out=B_in;end

S_3: begin next_state=S_5;B_out=B_in;end

S_4:if(B_in==0) begin next _state =S_5;B_out=1; end

Else if(B_in==1) begin next_state=S_6;end

S_5: begin next_state=S_0;B_out=B_in;end

S_6: begin next_state=S_0;B_out=1;end

/*Omitted for BCD_to_Xcess_3b_V2001 version

Included for BCD_to_Xcess_3b_V2001 version

Default :begin next_state=don’t_care_state;B_out_care_out;end

End case

End

endmodule