Create a Verilog module for a Mealy version of the same mach

Create a Verilog module for a Mealy version of the same machine that can report the number of ones in the current and last 127 bits on a synchronous serial input. Please minimize the critical paths from input or clock to output.

Solution

module mealy_detector ( x, en, clk, rst, z );
input x, en, clk, rst;
output z;
reg z;
parameter [1:0] reset = 0, got1 = 1, got10 = 2, got11 = 3;
reg [1:0] p_state, n_state;
always @( p_state or x ) begin : Transitions
n_state = reset;
case ( p_state )
reset: if ( x == 1\'b1 ) n_state = got1;
else n_state = reset;
got1: if ( x == 1\'b0 ) n_state = got10;
else n_state = got11;
got10: if ( x == 1\'b1 ) n_state = got1;
else n_state = reset;
got11: if ( x == 1\'b1 ) n_state = got11;
else n_state = got10;
default: n_state = reset;
endcase
end
always @( p_state or x ) begin: Outputting
z = 0;
case ( p_state )
reset: z = 1\'b0;
got1: z = 1\'b0;
got10: if ( x == 1\'b1 ) z = 1\'b1;
else z = 1\'b0;
got11: if ( x==1\'b1 ) z = 1\'b0;
else z = 1\'b1;
default: z = 1\'b0;
endcase
end

always @ ( posedge clk ) begin: Registering
if( rst ) p_state = reset;
else if( en ) p_state = n_state;
end

endmodule