Parity generatorchecker is commonly used to detect errors in

Parity generator/checker is commonly used to detect errors in data communication. \"Even\' parity output, OP, goes high when an even number of data inputs among 10 through 17 are high. Write a Verilog code to implement such an even parity generator using primitive gates.

Solution

module parity_checker32(a, y);

input [31:0] a;

output [32:0] y;

reg [32:0]y;

reg even=0;

reg odd=1;

integer i,count;

always @(a)

begin

count<=0;

for(i=10;i<=17;i=i+1)

begin

if(a[i]==1)

count<=count+1;

end

if(count%2==0)

begin

y<={even,a};

$display(\"even parity\");

end

else

begin

y<={odd,a};

$display(\"odd parity\");

end

end

endmodule