1 When testing it is important to have controllability and o

1) When testing it is important to have controllability and observability. What do these two
terms mean?

2) A digital design uses all of the resources in a PAL16R8. How many test patterns are needed
to exhaustively test this design?

3) A sequential digital circuit is implemented in an FPGA. You want to make the design scan
testable. What modifications are required to make this design scan-testable?

4) What are two ways that you can minimize crosstalk problems in PCBs?

5) Briefly explain why clock pulses sent down traces on a PCB are subject to distortion. (Do not
consider crosstalk or clock skew when answering this question.)

Solution

1) Controllability: In order to be able to do whatever we want with the given dynamic system under control input, the system must be controllable.

Observability: In order to see what is going on inside the system under observation, the system must be observable.

2) There are two test patterns are needed to exhaustively test this design.

3) Design for testability (DFT) makes it possible to:

We will focus on DFT techniques for digital logic, although it is relevant for memory and analog/mixed-signal components as well. An example chip level DFT technique is called Built-in self-test (BIST) (used for digital logic and memory.) At the system level, DFT includes boundary scan and analog test bus. The DFT techniques discussed focus on improving testability of SAFs. DFT for other fault models, e.g., delay faults.

Two forms of DFT: ad-hoc and structured.

Ad-hoc DFT relies on \"good\" design practices:

Testability measures can be used to identify circuit areas that are difficult to test. Once identified, circuit is modified or test points are inserted.

This type of ad-hoc strategy is difficult to use in large circuits:

Structured DFT involves adding extra logic and signals dedicated for test according to some procedure. The circuit has two modes, normal and test mode. The most commonly used structured methods are Scan and BIST.

4) Capacitive Crosstalk or Coupling

Inductive Crosstalk

Minimize crosstalk by