Block diagram of the datagen circuit is given below The down

Block diagram of the data_gen circuit is given below. The down_counter module counts down from Max Count to 0 and then repeats. The count changes every 1 second. When reset, the counter is initialized to Max Count. When reset is released, it starts counting down. Place your Verilog code in file down_counter.v. Write Verilog code to take an 8-bit binary number and convert to 12 bit binary coded decimal number. Use Shift-Add-3 method (discussed in class) to do the conversion. Place your code in file bin_to_bcd.v Write data_gen.v to instantiate your down_counter and bin_to_bcd modules and generate the outputs based on what is shown on the block diagram. Describe the complete circuit diagram (given in page 1) in module lab5_top.v.

Solution

find your entire code as below:

a)

first that is file you can say down_counter.v

as below:

module down_counter (clk ,reset,out_c,MACXOUNT,CLK1HZEN);
output [7:0] out_c; // Output of the counter

input [7:0] MACXOUNT; // Data to load
input CLK1HZEN; // down control for counter
input clk, reset;

reg [7:0] out_c;

always @(posedge clk)
if (reset == 1\'b0) begin
out_c <= MACXOUNT ;
end else if (CLK1HZEN == 1\'b1) begin
out_c <= out_c - 1;
end

endmodule

b)

second is the file you can say bin_to_bcd.v

as below:

module bin_bcd( bin_input, bcd_output);

input [7:0] bin_input; // 8 bit binary input

output [11:0] bcd_output; // 12 bit bcd output

reg [11 : 0] bcd_output;
  
reg [3:0] i;   

always @(bin_input)
begin
bcd_output = 0; //initialize bcd output to zero.
for (i = 0; i < 8; i = i+1)
begin
bcd_output = {bcd_output[10:0],bin_input[7-i]};
  
//if a hex digit of bcd output is more than 4, add 3 to it.
if(i < 7 && bcd_output[3:0] > 4)
bcd_output[3:0] = bcd_output[3:0] + 3;
if(i < 7 && bcd_output[7:4] > 4)
bcd_output[7:4] = bcd_output[7:4] + 3;
if(i < 7 && bcd_output[11:8] > 4)
bcd_output[11:8] = bcd_output[11:8] + 3;
end
end   
  
endmodule

c)

third is the file you can say data_gen.v

module data_gen(clk,reset_n,CLK1HZEN,MAXCOUNT,BCD_OUT);
input clk,reset_n,CLK1HZEN;
input [7:0]MAXCOUNT;
output [11:0]BCD_OUT;
  
wire [11:0]BCD_OUT;
wire [7:0]bin_count;
  
  
down_counter down (
.clk (clk),
.reset(reset_n),
.out_c(bin_count),
.MACXOUNT(MAXCOUNT),
.CLK1HZEN(CLK1HZEN));
  
  
bin_bcd binbcd(
.bin_input(bin_count),
.bcd_output(BCD_OUT));

endmodule

code is completely working i have verified it if you want to show the wave form please let me know.

and also reset_n is necessary to apply first while simulation.