For the following twenty 32bit signed integers in the data m

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6.4 Move Instructions: The Move instructions copy the contents of one register into another, or they place an immediate value into a register. They are pseudoinstructions implemented by using other instructions. The instruction mov rC, rA copies the contents of register A into register C. It is implemented as add rC, rA, r0 The Move Immediate instruction movi rB, IMMED16 sign extends the IMMED16 value to 32 bits and loads it into register B. It is implemented as addi rB, r0, IMMED16 The Move Unsigned Immediate instruction 10 movui rB, IMMED16 zero extends the IMMED16 value to 32 bits and loads it into register B. It is implemented as ori rB, r0, IMMED16 The Move Immediate Address instruction movia rB, LABEL loads a 32-bit value that corresponds to the address LABEL into register B. It is implemented as: orhi rB, r0, %hi(LABEL) ori rB, rB, %lo(LABEL) The %hi(LABEL) and %lo(LABEL) are the Assembler macros which extract the high-order 16 bits and the loworder 16 bits, respectively, of a 32-bit value LABEL. The orhi instruction sets the high-order bits of register B, followed by the ori instruction which sets the low-order bits of B. Note that two instructions are used because the I-type format provides for only a 16-bit immediate operand. 6.5 Comparison Instructions The Comparison instructions compare the contents of two registers or the contents of a register and an immediate value, and write either 1 (if true) or 0 (if false) into the result register. They are of R-type or I-type, respectively. These instructions correspond to the equality and relational operators in the C programming language. The Compare Less Than Signed instruction cmplt rC, rA, rB performs the comparison of signed numbers in registers A and B, rA < rB, and writes a 1 into register C if the result is true; otherwise, it writes a 0. The Compare Less Than Unsigned instruction cmpltu rC, rA, rB performs the same function as the cmplt instruction, but it treats the operands as unsigned numbers. Other instructions of this type are: • cmpeq rC, rA, rB (Comparison rA == rB) • cmpne rC, rA, rB (Comparison rA != rB) • cmpge rC, rA, rB (Signed comparison rA >= rB) • cmpgeu rC, rA, rB (Unsigned comparison rA >= rB) • cmpgt rC, rA, rB (Signed comparison rA > rB) This is a pseudoinstruction implemented as the cmplt instruction by swapping its rA and rB operands. • cmpgtu rC, rA, rB (Unsigned comparison rA > rB) This is a pseudoinstruction implemented as the cmpltu instruction by swapping its rA and rB operands. • cmple rC, rA, rB (Signed comparison rA <= rB) This is a pseudoinstruction implemented as the cmpge instruction by swapping its rA and rB operands. • cmpleu rC, rA, rB (Unsigned comparison rA <= rB) This is a pseudoinstruction implemented as the cmpgeu instruction by swapping its rA and rB operands. 11 The immediate versions of the Comparison instructions involve an immediate operand. For example, the Compare Less Than Signed Immediate instruction cmplti rB, rA, IMMED16 compares the signed number in register A with the sign-extended immediate operand. It writes a 1 into register B if rA < IMMED16; otherwise, it writes a 0. The Compare Less Than Unsigned Immediate instruction cmpltui rB, rA, IMMED16 compares the unsigned number in register A with the zero-extended immediate operand. It writes a 1 into register B if rA < IMMED16; otherwise, it writes a 0. Other instructions of this type are: • cmpeqi rB, rA, IMMED16 (Comparison rA == IMMED16) • cmpnei rB, rA, IMMED16 (Comparison rA != IMMED16) • cmpgei rB, rA, IMMED16 (Signed comparison rA >= IMMED16) • cmpgeui rB, rA, IMMED16 (Unsigned comparison rA >= IMMED16) • cmpgti rB, rA, IMMED16 (Signed comparison rA > IMMED16) This is a pseudoinstruction which is implemented by using the cmpgei instruction with an immediate value IMMED16 + 1. • cmpgtui rB, rA, IMMED16 (Unsigned comparison rA > IMMED16) This is a pseudoinstruction which is implemented by using the cmpgeui instruction with an immediate value IMMED16 + 1. • cmplei rB, rA, IMMED16 (Signed comparison rA <= IMMED16) This is a pseudoinstruction which is implemented by using the cmplti instruction with an immediate value IMMED16 + 1. • cmpleui rB, rA, IMMED16 (Unsigned comparison rA <= IMMED16) This is a pseudoinstruction which is implemented by using the cmpltui instruction with an immediate value IMMED16 + 1. 6.6 Shift Instructions The Shift instructions shift the contents of a register either to the right or to the left. They are of R-type. They correspond to the shift operators, >> and <<, in the C programming language. These instructions are: • srl rC, rA, rB (Shift Right Logical) • srli rC, rA, IMMED5 (Shift Right Logical Immediate) • sra rC, rA, rB (Shift Right Arithmetic) • srai rC, rA, IMMED5 (Shift Right Arithmetic Immediate) • sll rC, rA, rB (Shift Left Logical) • slli rC, rA, IMMED5 (Shift Left Logical Immediate) 12 The srl instruction shifts the contents of register A to the right by the number of bit positions specified by the five least-significant bits (number in the range 0 to 31) in register B, and stores the result in register C. The vacated bits on the left side of the shifted operand are filled with 0s. The srli instruction shifts the contents of register A to the right by the number of bit positions specified by the five-bit unsigned value, IMMED5, given in the instruction. The sra and srai instructions perform the same actions as the srl and srli instructions, except that the sign bit, rA31, is replicated into the vacated bits on the left side of the shifted operand. The sll and slli instructions are similar to the srl and srli instructions, but they shift the operand in register A to the left and fill the vacated bits on the right side with 0s. 6.7 Rotate Instructions There are three Rotate instructions, which use the R-type format: • ror rC, rA, rB (Rotate Right) • rol rC, rA, rB (Rotate Left) • roli rC, rA, IMMED5 (Rotate Left Immediate) The ror instruction rotates the bits of register A in the left-to-right direction by the number of bit positions specified by the five least-significant bits (number in the range 0 to 31) in register B, and stores the result in register C. The rol instruction is similar to the ror instruction, but it rotates the operand in the right-to-left direction. The roli instruction rotates the bits of register A in the right-to-left direction by the number of bit positions specified by the five-bit unsigned value, IMMED5, given in the instruction, and stores the result in register C. 6.8 Branch and Jump Instructions The flow of execution of a program can be changed by executing Branch or Jump instructions. It may be changed either unconditionally or conditionally. The Jump instruction jmp rA transfers execution unconditionally to the address contained in register A. The Unconditional Branch instruction br LABEL transfers execution unconditionally to the instruction at address LABEL. This is an instruction of I-type, in which a 16-bit immediate value (interpreted as a signed number) specifies the offset to the branch target instruction. The offset is the distance in bytes from the instruction that immediately follows br to the address LABEL. Conditional transfer of execution is achieved with the Conditional Branch instructions, which compare the contents of two registers and cause a branch if the result is true. These instructions are of I-type and the offset is determined as explained above for the br instruction. 13 The Branch if Less Than Signed instruction blt rA, rB, LABEL performs the comparison rA < rB, treating the contents of the registers as signed numbers. The Branch if Less Than Unsigned instruction bltu rA, rB, LABEL performs the comparison rA < rB, treating the contents of the registers as unsigned numbers. The other Conditional Branch instructions are: • beq rA, rB, LABEL (Comparison rA == rB) • bne rA, rB, LABEL (Comparison rA != rB) • bge rA, rB, LABEL (Signed comparison rA >= rB) • bgeu rA, rB, LABEL (Unsigned comparison rA >= rB) • bgt rA, rB, LABEL (Signed comparison rA > rB) This is a pseudoinstruction implemented as the blt instruction by swapping the register operands. • bgtu rA, rB, LABEL (Unsigned comparison rA > rB) This is a pseudoinstruction implemented as the bltu instruction by swapping the register operands. • ble rA, rB, LABEL (Signed comparison rA <= rB) This is a pseudoinstruction implemented as the bge instruction by swapping the register operands. • bleu rA, rB, LABEL (Unsigned comparison rA <= rB) This is a pseudoinstruction implemented as the bgeu instruction by swapping the register operands.

6.1 Load and Store Instructions Load and Store instructions are used to move data between memory (and I/0 interfaces) and the general purpose registers. They are of I-type. For example, the Load Word instruction ldw rB, byte_offset(rA) 7 determines the effective address of a memory location as the sum of a byte_offset value and the contents of register A. The 16-bit byte_offset value is sign extended to 32 bits. The 32-bit memory operand is loaded into register B. For instance, assume that the contents of register r4 are 126010 and the byte_offset value is 8010. Then, the instruction ldw r3, 80(r4) loads the 32-bit operand at memory address 134010 into register r3. The Store Word instruction has the format stw rB, byte_offset(rA) It stores the contents of register B into the memory location at the address computed as the sum of the byte_offset value and the contents of register A. There are Load and Store instructions that use operands that are only 8 or 16 bits long. They are referred to as Load/Store Byte and Load/Store Halfword instructions, respectively. Such Load instructions are: • ldb (Load Byte) • ldbu (Load Byte Unsigned) • ldh (Load Halfword) • ldhu (Load Halfword Unsigned) When a shorter operand is loaded into a 32-bit register, its value has to be adjusted to fit into the register. This is done by sign extending the 8- or 16-bit value to 32 bits in the ldb and ldh instructions. In the ldbu and ldhu instructions the operand is zero extended. The corresponding Store instructions are: • stb (Store Byte) • sth (Store Halfword) The stb instruction stores the low byte of register B into the memory byte specified by the effective address. The sth instruction stores the low halfword of register B. In this case the effective address must be halfword aligned. Each Load and Store instruction has a version intended for accessing locations in I/O device interfaces. These instructions are: • ldwio (Load Word I/O) • ldbio (Load Byte I/O) • ldbuio (Load Byte Unsigned I/O) • ldhio (Load Halfword I/O) • ldhuio (Load Halfword Unsigned I/O) • stwio (Store Word I/O) • stbio (Store Byte I/O) • sthio (Store Halfword I/O)