Register File in Verilog Inputs WriteEnable Clock In140 In24

Register File in Verilog

Inputs: WriteEnable, Clock, In1[4:0], In2[4:0], Reg[4:0], Data[31:0]

Outputs: Out1[31:0], Out2[31:0]

The register file is required to contain thirty-two 32-bit registers. Out1 has to be the value of the register specified by the index applied in binary to In1. The same goes for Out2 and In2, respectively. For example, if In1 is 01101, then Out1 is the 32-bit value storing in register 13. Both outputs must be updated as soon as In1 or In2 change; they do not wait for the clock edge. If the write enable input is true when the Clock transitions from 0 to 1 (i.e. positive edge), the Data value is stored into the register specified by the binary value applied to Reg.

I\'m having a hard time even starting this assignment. Any help would be greatly appreciated!

Solution

Find the verilog code as below:

module regfile(WriteEnable,Clock,In1,In2,register,Data,Out1,Out2);

input WriteEnable,Clock;
input [4:0]In1,In2;
input [4:0]register;   
input [31:0]Data;

output [31:0]Out1,Out2;
reg [31:0]Out1,Out2;

reg [31:0]regfileq[0:31]; //regfile of 32 register with 32 bits register

always @(negedge Clock,In1,In2)

begin
  
if(WriteEnable == 1)begin //if negegde of clock and writeenable is 1 data is stored in regfile
regfileq[register] <= Data;
$display (\"---regfileq[%d]=%h\",register,regfileq[register]);
end

Out1 <= regfileq[In1]; // if either change in In1 or In2 it doesnot wait for a clcok and
Out2 <= regfileq[In2]; // assign values to Out1 and Out2
$display (\"---Out1=%h\",Out1);
$display (\"---Out2=%h\",Out2);
end

endmodule