VHDL Write VHDL code to describe the absolute value circuit

VHDL: Write VHDL code to describe the absolute value circuit from Exercise 4, using k = 8 bits. The VHDL module should be called Problem 4, it should accept two 8-bit inputs called A and B, and produce one 8-bit output Y which is the absolute value of A + B. Your solution should include both a schematic and the corresponding VHDL code. You can access the most significant bit of an 8-bit signal S by writing S(7).

Solution

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use ieee.std_logic_unsigned.all;
entity problem4 is
port(A,B:in std_logic_vector(7 downto 0);
Sum:out std_logic_vector(7 downto 0));
end problem4;
architecture BEH of problem4 is

begin

Sum<=A+B;
  
end BEH;