Digital logic design The unsigned integer multiplier operati

The unsigned integer multiplier operation defined by y = a * b where a and b are 4-bit unsigned binary number, and * denoted multiplication. Start by writing the truth table for the multiplier and then convert the truth Start by writing the truth table for the multiplier and then convert the truth table to VHDL. Use IEEE 1164 logic.

Solution

a3 a2 a1 a0 b3 b2 b1 b0 y7 y6 y5 y4 y3 y2 y1 y0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \" \" 0 0 0 1 0 0 0 0 0 0 0 0 0 -- - - -- -- -- -- 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 \"\" 0 0 0 1 0 0 0 0 0 0 0 1 -- -- -- -- -- -- 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 -- -- -- -- -- -- 0 0 1 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 \"\" 0 0 0 1 0 0 0 0 0 0 1 1 -- -- -- -- -- -- 0 0 1 1 1 1 1 1 0 0 1 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \"\" 0 0 0 1 0 0 0 0 0 1 0 0 -- -- -- -- -- -- 0 1 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 \"\" 0 0 0 1 0 0 0 0 0 1 0 -1 -- -- -- -- -- -- 0 1 0 1 1 1 1 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 \"\" 0 0 0 1 0 0 0 0 0 1 1 0 -- -- -- -- -- -- 0 1 1 0 1 1 1 1 0 1 0 1 1 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 \"\" 0 0 0 1 0 0 0 0 0 1 1 1 -- -- -- -- -- -- 0 1 1 1 1 1 1 1 0 1 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \" \" 0 0 0 1 0 0 0 0 0 1 0 0 0 -- - - -- -- -- -- 1 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 \" \" 0 0 0 1 0 0 0 0 0 1 0 0 1 -- - - -- -- -- -- 1 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \" \" 0 0 0 1 0 0 0 0 0 1 0 1 0 -- - - -- -- -- -- 1 0 1 0 1 1 1 1 1 0 0 1 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 \" \" 0 0 0 1 0 0 0 0 0 1 0 1 1 -- - - -- -- -- -- 1 0 1 1 1 1 1 1 1 0 1 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \" \" 0 0 0 1 0 0 0 0 0 1 1 0 0 -- - - -- -- -- -- 1 1 0 0 1 1 1 1 1 0 1 1 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 \" \" 0 0 0 1 0 0 0 0 0 1 1 0 1 -- - - -- -- -- -- 1 1 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \" \" 0 0 0 1 0 0 0 0 0 1 1 1 0 -- - - -- -- -- -- 1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 \" \" 0 0 0 1 0 0 0 0 0 1 1 1 1 -- - - -- -- -- -- 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity Mul_VHDL is port ( a, b: in std_logic_vector(3 downto 0); y: out std_logic_vector(7 downto 0) ); end entity Mul_VHDL; architecture Behavioral of Mul_VHDL is begin y <= std_logic_vector(unsigned(a) * unsigned(a)); end architecture Behavioral;