Write a selfchecking VHDL testbench for Exercise 2 43 Create

Write a self-checking VHDL testbench for Exercise 2 (4.3). Create and load a test vector file containing all 16 test cases which provides stimulus to your XOR HDL nodule. Run you test bench showing the output results for a successful test. Introduce an error in the test vector file and show that the testbench reports a mismatch. Notes on testvector files Here are some tips if you get error messages about opening the text vector file. The different tools can be picky and have different requirements Use FILE_CLOSE() to close the file after you\'re code is done with it. Try using the full path, only the basic file name or a short file name of the test vector file and don\'t include it as a project file. If you make any changes such as the above and it still doesn\'t work, create a new project directory and workspace. Notes on language version If you get on error about XOR, try one of the following (depending on your tool and version). Right click on the, vhd file want to compile. On the pull down menu, select \"Properties...\". Then select \"VHDL\" tab. Then choose \"use 1076-2008\" in \"Language Syntax\" Compile rightarrow Compile Options... Then select the \"Use 1076-2008\" radio button, and click \'Apply\'.

Solution

The self-checking testbench produced by this procedure is only to be used for behavioral simulation. Using the self-checking testbench created for behavioral simulation to perform timing simulation can generate simulation errors.
Create a test bench waveform file. Image
Select File > Save to add the test bench waveform file to your project.
Edit your design and test bench waveforms as needed.
In the Sources tab, select Behavioral Simulation from the drop-down list. Image
Run behavioral simulation on your design with the test bench waveform file. Image
Repeat Steps 3 and 5 until you are satisfied with the simulation results. The design resulting from these steps is called the \"golden\" design.
To Generate a Self-Checking Test Bench

--import std_logic from the IEEE library
library ieee;
use ieee.std_logic_1164.all;

--ENTITY DECLARATION: no inputs, no outputs
entity xorGate_tb is
end xorGate_tb;

-- Describe how to test the XOR Gate
architecture tb of xorGate_tb is
--pass xorGate entity to the testbench as component
component xorGate is  
port( A, B : in std_logic;
F : out std_logic);
end component;

signal inA, inB, outF : std_logic;
begin
--map the testbench signals to the ports of the xorGate
mapping: xorGate port map(inA, inB, outF);

process
--variable to track errors
variable errCnt : integer := 0;
begin
--TEST 1
inA <= \'0\';
inB <= \'0\';
wait for 15 ns;
assert(outF = \'0\') report \"Error 1\" severity error;
if(outF /= \'0\') then
errCnt := errCnt + 1;
end if;

--TEST 2
inA <= \'0\';
inB <= \'1\';
wait for 15 ns;
assert(outF = \'1\') report \"Error 2\" severity error;
if(outF /= \'1\') then
errCnt := errCnt + 1;
end if;

--TEST 3
inA <= \'1\';
inB <= \'1\';
wait for 15 ns;
assert(outF = \'0\') report \"Error 3\" severity error;
if(outF /= \'0\') then
errCnt := errCnt + 1;
end if;

-------------- SUMMARY -------------
if(errCnt = 0) then
assert false report \"Good!\"   severity note;
else
assert true report \"Error!\"   severity error;
end if;

end process;
end tb;
--------------------------------------------
configuration cfg_tb of xorGate_tb is
for tb
end for;
end cfg_tb;
---------------------------------------------------------END
---------------------------------------------------------END

In the Sources tab, select the test bench waveform file for which you will generate the self-checking test bench.
In the Processes tab, expand Xilinx ISE Simulator, then expand Simulate Behavioral Model.
Right-click the Generate Self-Checking Test Bench process, and select Properties.
Set the property values in the Process Properties dialog box.
For the ISim, you can set the ISim Properties in the Process Properties dialog box.
For the ModelSim simulator, you can set the Simulation Properties in the Process Properties dialog box.
Double-click Generate Self-Checking Test Bench.
A self-checking test bench is generated and added to your project.
The self-checking test bench is named waveform_file_name_selfcheck_beh.v (Verilog) or waveform_file_name_selfcheck_beh.vhd (VHDL). If you run the process again, you will be prompted to either overwrite the previous self-checking test bench or create a new file, iterating each time (filename_0.vhd, filename_1.vhd, etc.).