Homework Soursewas wondering if you could help me with this problem 1 Desig
was wondering if you could help me with this problem: 1) Design a block of memory that is 512K x 8 bits using chips that are 128k x 8 bits. Assume that the chips are ROM with Chip Enable inputs, and Output Enable inputs. How many address inputs do the individual chips have? How many total address lines are needed to decode the entire 512K? Show the decoder and indicate which address liens are used as its inputs and show how its outputs are to be used. Assume that the microprocessor has a 24-bit address bus and design decoding logic to place your memory block at a base address of 0xD80000. Assume that the processor has a clock period of 5ns and memory chips’ access time is 58ns. Design a (DTACK) circuit that will generate the correct number of wait states.
was wondering if you could help me with this problem: 1) Design a block of memory that is 512K x 8 bits using chips that are 128k x 8 bits. Assume that the chips are ROM with Chip Enable inputs, and Output Enable inputs. How many address inputs do the individual chips have? How many total address lines are needed to decode the entire 512K? Show the decoder and indicate which address liens are used as its inputs and show how its outputs are to be used. Assume that the microprocessor has a 24-bit address bus and design decoding logic to place your memory block at a base address of 0xD80000. Assume that the processor has a clock period of 5ns and memory chips’ access time is 58ns. Design a (DTACK) circuit that will generate the correct number of wait states.
was wondering if you could help me with this problem: 1) Design a block of memory that is 512K x 8 bits using chips that are 128k x 8 bits. Assume that the chips are ROM with Chip Enable inputs, and Output Enable inputs. How many address inputs do the individual chips have? How many total address lines are needed to decode the entire 512K? Show the decoder and indicate which address liens are used as its inputs and show how its outputs are to be used. Assume that the microprocessor has a 24-bit address bus and design decoding logic to place your memory block at a base address of 0xD80000. Assume that the processor has a clock period of 5ns and memory chips’ access time is 58ns. Design a (DTACK) circuit that will generate the correct number of wait states.
Solution
128 x 8 RAM => 128 Bytes (8bits) / chip => Nbr of chips = 2048 / 128 = 16
Memory size is 1024 bytes = 8 x 1024 x 1 RAM => 8 chips
All has same address lines and output is one bit from every chip. you will get the wait states with respect to the
The access times should be divided by the period and
rounded down to obtain the nu
mber of wait states.
Initial Access: 90/7.52 - 11 wait
states 100/7.52 =13 wait states
Page Access: 25/7.52 = 3 wait
states 30/7.52 = 3 wait states
here i gave some examples how to calculate the wait states for different ns so please do the required as above.
