What is the typical FPGA hardware design flow when VHDL is u

What is the typical FPGA hardware design flow when VHDL is used as the design entry? In an FPGA, memories can be implemented using Distributed RAM or Block RAM. What is the difference between these two types? Can a 4-input Look-Up Table be used to implement the logic functions shown in Fig. 1(c)? Justify your answer. How many 4-input Look-Up Tables would be consumed to implement: a 16 by 2-bit Distributed RAM a 16 by 2-bit Block RAM

Solution

a) When designing a circuit to be implemented in a FPGA, following steps are followed in the specified order:

1. Design Specifications: First of all, the requirements of the design and specifications to be complied are listed down.

2. Initial Design: Thereafter a rough design is drafted which will further be tested, changed and again tested till it meets the specifications. This design is basically in the form of digital logic or block diagrams.

3. VHDL Code: Thereafter a VHDL Code is written to realize our initial Design.

4. Functional Simulation: After the VHDL Code is written, a functional simulation is done to verify whether our design is functionally correct or not. If not, then the initial Design is changed to meet the requirements.

5. Timing Simulation: Once our design is functionally correct, we go for a timing simulation. Here we verify that once our design will be implemented on FPGA, will it verify the various timing requirements or not such as setup time, hold time, maximum allowable delay. This simulation depends on actual placement of logic blocks and is hardware dependent.

6. Configuration file: Once the design is found to be correct in functionality and timing requirements, we generate the configuration file for our FPGA hardware. Thus file is used to program the device.

7. Design Realization: Finally the configuration file is downloaded in the FPGA board via appropriate programmer and we are good to go.

b) Block RAM is a dedicated block of memory in the FPGA which is solely used as a RAM. On the other hand, distributed RAM is implanted in the FPGA using the Look up tables (LUTs) in each Configurable Logic Block (CLB). Normally LUTs are used to implement some logic function, but they can also be used as distributed memory since each LUT has memory.

Block RAM is a dedicated section for RAM and hence is efficient in terms of space requirements. But distributed RAM is much closer to the logic blocks and hence is faster. It is a good option for small amount of memory requirements, boot memory etc.

c) A 4 input look up table has 4 inputs and one output. Output is a function of the four inputs. There are 2^4=16 entries in the table.

i) For the first circuit, there are 4 inputs but 2 outputs. But we can implement only a single output in one LUT. Hence we can\'t implement this circuit in one 4 input LUT. We will require 2 such LUTs to implement this circuit.

ii) Second circuit has 4 inputs and 1 output. It can easily be implemented in a LUT. It\'s truth table can be written down and stored in the LUT.

iii) Third circuit has only two inputs. Hence it can very easily be implemented in a 4 input LUT. But a better option will be to use a 2 input LUT for this for effective use of resources.

d) Assuming a 4 input look up table with a single output:

i) To implement a 16 by 2 bits distributed RAM, two such LUTs will be required. One for the first bit, other for the second.

ii) Logically block RAM is same as a distributed RAM. Both are used to store memory. Difference lies in way of implementation. If a 4 input LUT is used to implement a 16 by 2 bits RAM, it will require 2 such LUTs.