5 With the help of the template in Hall Appendix A1 show the

5. With the help of the template in Hall Appendix A1, show the LABELED machine code for the XScale instruction ADDEQ R3.RZ.R9. (Remember shift bits all 0\'s) 31 0|0|0|0|0|0|0|0|1|0|0|0|0|1|1|1|0|0|1|1|0|0|00|0|0|0|0|1|0|0|1 Cond op STId l rm 5. With the help of the template in Hall Appendix A1, show the LABELED machine code for the XScale instruction EORSNE R1R5. R4·(Remember shift bits all 0\'s) 31 0 01 0 0 ! SRC 2 0001000 00 011010100 01 COND ! FIXED OP !s! SRC1 ! DEST SHIFT 5. With the help of the template in Hall Appendix A1, show the LABELED machine code for the XScale instruction SUBSEQ R1,R2, R3. (Remember shift bits all 0\'s) 31 0|0|0|0|0|0|0|0|0|1|0|1|0|0|1|0|0010|1|0|0|0|0|0|0|0|0|0|0|1|1 COND ! EIXEDL OP !s! SRC1 ! DEST SHIFT ! SRC 2 5. With the help of the template in Hall Appendix A1, show the labeled machine code for the XScale instruction ANDNE R7.R4, R5. (Remember shift bits all 0\'s) 31 Cond 0 op TST Irdl l rm 5. For the ARM ANDEQR3.RTR9 instruction, the 4-bit condition code that the assembler would insert in the 32-bit code for this instruction is 0000

Solution

Rm,Rn,Rd are three registers.

For any instruction we write code as

opcode Rd,Rn,Rm

For example ANDEQ R3,R7,R9

Write opcode for ANDEQ

Rd=R3,Rn=R7,Rm=R9 that is

Rd=0011,Rn=0111,Rm=1001

S indicates status of condition code flags when it is specified in instruction

For example ANDS R3,R5,R7

S=1 because it is in instruction where as

ANDEQ R3,R5,R7 S=0.