Question 5 Write the complete VHDL code to implement a 4bit

Question 5

Write the complete VHDL code to implement a 4-bit up/down counter with synchronous reset and synchronous parallel load. Include the appropriate library declaration and the complete entity and architecture declarations. Use a positive edge triggered clock CLK. The counter should reset when RESETn=0 and be loaded with parallel data DIN when LOAD=1. Resetting has priority over loading data. The counter should count up when UPDOWN=1 and count down when UPDOWN=0.

Solution

find the VHDL code as below:

library IEEE;  
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity updown_counter is
port(DIN : in std_logic_vector(0 to 3);
CLK: in std_logic;
LOAD: in std_logic;
RESETn: in std_logic;
UPDOWN: in std_logic;
Output: out std_logic_vector(0 to 3) );
end updown_counter;

architecture Behavioral of updown_counter is
signal temp: std_logic_vector(0 to 3);
begin
process(CLK)
begin
if ( CLK\'event and CLK=\'1\') then
if RESETn=\'0\' then
temp <= \"0000\";
if LOAD=\'1\' then
temp <= DIN;
elsif (Load=\'0\' and UPDOWN=\'1\') then
temp <= temp + 1;
elsif (Load=\'0\' and UPDOWN=\'0\') then
temp <= temp - 1;
end if;
end if;
end if;
end process;
Output <= temp;
end Behavioral;