Consider a 1GHz processor with singlelevel split instruction

Consider a 1GHz processor with single-level, split instruction and data caches. Both caches are write-through with write buffers (assuming write buffer does not stall and non-allocation for write miss), and have single-cycle hit time and 32-Byte blocks. Assuming there is no L2 cache. Main memory is interleaved, with 4 independent 8-Byte memory banks and a 50ns latency. The memory bus is 8 Bytes wide and has a clock frequency of ¼ of the processor frequency. The instruction cache miss rate is 0.1% and the data cache miss rate is 5% for loads, and 5% for stores. Assume 20% of the instructions are loads and 10% are stores. Determine a)The miss penalty. b) The average memory access time. c) The average number of bytes transferred on the bus (between memory and cache) for every 100 instructions executed. (Assuming every store write 32bit information)

Solution

32 bits