Complete the timing diagram of the following circuit G G3G2

Complete the timing diagram of the following circuit. G = G_3G_2G_1_0 = 1101, Q = Q_3Q_2Q_1Q_0

Solution

from the circuit , the output is calulated at each positive clock triggering.

at each AND GATE the output is A₀ A₁ A₂ A₃    (ASSUMPION )

the input to the flipflop is output of XOR GATE that is assumed as D₀ D₁ D₂ D₃

   

CLK

NUMBER

the output at each positive edge clock cycle as shown above

the truth table of AND GATE is below (generalized)

TRUTH TABLE OF XOR GATE

TRUTH TABLE OF D FLIPFLOP

CLOCK

RESET

ENABLE

X

PREVIOUS OUTPUT

AND GATE INPUT

AND GATE OUTPUT

PRESENT INPUT

PRESENT OUTPUT