Homework Soursecould you please create a shift register with parallel load
could you please create a shift register with parallel load, shift right and shift left functions using VHDL. See step 5 in pages 5 and 6.
Your task: Create a shift register with parallel load, shift right and shift left functions using VHDL.
1) The symbol should look like as follows:
Where Cp - the rising edge triggered clock,
s1, s0 - mode control,
dsr - the serial data input for shift right
dsl - the serial data output for shift left
para_D[3..0] – 4-bit parallel data input
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q3, q2, q1, q0 – 4-bit data output The shift register should have four operating modes: S1 S0 Operation 0 0 hold 0 1 shift right 1 0 shift left 1 1 parallel load 2) After perform simulation and verify the functions successfully, download the program and test it in DE1 board. Please show the demo the instructor. Please use the following pin assignment for test purpose: Inputs: Switches or pushbuttons Outputs LEDs Cp key3 PIN_T21 q3 LEDR3 PIN_Y19 s1 SW9 PIN_L2 q2 LEDR2 PIN_U19 s0 SW8 PIN_M1 q1 LEDR1 PIN_R19 dsr SW5 PIN_U12 q0 LEDR0 PIN_R20 dsl SW4 PIN_W12 para_D[3..0] SW3 PIN_V2 SW2 PIN_M22 SW1 PIN_L21 SW0 PIN_L22
Solution
The VHDL program for the shift register with the given requirements is shown below:
library IEEE;
use IEEE.std_logic_1164.all;
entity shiftregister is
port (CP : in STD_LOGIC;--Clock signal
dsr,dsl : in STD_LOGIC;--serial input for right shift and left shift
s:in STD_LOGIC_VECTOR(2 downto 0);--mode control bits
D: in unsigned (3 downto 0);--4-bit parallel input bits
q: inout unsigned (3 downto 0)); --4-bit output
end shiftregister;
architecture shiftregister of shiftregister is
begin
process(clk)
begin
if(clk\'event and clk=\'1\') then
case s is
when\"00\" =>q<=q;--Hold the data on output lines
when\"01\" => q<=dsr & q(3 downto 1);--shift right
when\"10\" => q<=q(2 downto 0) & dsl;--shift left
when\"11\"=>q<=d; --parallel load
when others=>null;
end case;
end if;
end process;
end shiftregister;
