Answer the questions that follow the VHDL code given below L

Answer the questions that follow the VHDL code given below. LIBRARY ieee; USE ieee.std_logic_1164. ALL; ENTITY ex1_IS PORT(n_cp, n_rd) END ex1; ARCHITECTURE are OF ex 1 IS BEGIN PROCESS (n_cp, n_rd) BEGIN IF (n_rd=\'0\') THEN q

Solution

a)its peroform upcounter opereation

b)its mod-11 counter

c)its perform the operation in negative edge of the clock

d)negedge(n_cp)