Write structural VHDL code for a module that has two inputs

Write structural VHDL code for a module that has two inputs: an N-bit vector A, and

a control signal B (1 bit). The module has an N-bit output vector, C. When B 1, C

A. When B 0, C is all 0’s. Use a generic to specify the value of N (default 4).

To implement the logic, use a generate statement that instantiates N 2-input AND

gates.

Solution

library ieee;
use ieee.std_logic_1164.all;
entity ex_genric is
generic (N : Integer := 4);
port (C: out Bit_Vector (0 to N-1);
A: in Bit_Vector (0 to N-1);
B: in Bit );
end entity ex_genric;
architecture BEH of ex_genric is
component AND2
port(A,B : in BIT; C : out BIT);
end component ;

begin
  
G_1 : for I in 0 to N-1 generate
AND_gate:
AND2 port map
(A(I), B, C(I));
end generate;
end architecture BEH;