Homework SourseDigital logic design Write the VHDL code entity and arch Usi
Solution
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity fsm is
port(rst : in std_logic;
clk : in std_logic;
input : in std_logic;
output : out std_logic);
end entity fsm;
architecture fsm_arc of fsm is
type state_type is (S4,S3,S2,S7,S0,S1,);
signal state : state_type;
begin
p1 : process(rst, clk)
begin
if(rst = \'1\')then
state <= S4,S3,S2,S7;
output <= \'0\';
if(clk\'event and clk = \'1\')then
case state is
when S4,S3,S2,S7=>
if(input = \'1\')then
state <= S3;
output <= \'0\';
else
state <= S4,S3,S2,S7;
output <= \'0\';
end if;
when S3=>
if(input = \'1\')then
state <= S0;
output <= \'0\';
else
state <= S2;
output <= \'0\';
end if;
when S0=>
if(input = \'1\')then
state <= S0;
output <= \'1\';
else
state <= S1;
output <= \'0\';
end if;
when S2=>
if(input = \'1\')then
state <= S1;
output <= \'1\';
else
state <= S2;
output <= \'0\';
end if;
end case;
end if;
end if;
end process p1 ;
end architecture fsm_arc;
