The code below was copied from a VHDL design file of a full

The code below was copied from a VHDL design file of a full adder. The is one erroncous statement in the architecture body. entity Full_Adder is port (A in STD_LOGIC; B: in STD_LOGIC; Cin: in STD_LOGIC; Cout: in STD_LOGIC; Sum: in STD_LOGIC; end Full_adder; architecture dataflow of Full_Adder is begin Sum

Solution

C) There is an error in the line 29. Because there is ambiguity in \"xor\" representation with lower case and upper case letters. This leads to error at line number 29.

D) This error can be fixed by writing smaller case letter in the place of \"XOR\" written in line number 29.