Convert the VHDL code to Verilog entity mux4 is port selmux

Convert the VHDL code to Verilog

entity mux4 is

port (sel_mux: in std_logic_vector(1 downto 0);

in3_mux,in2_mux,in1_mux,in0_mux: in std_logic_vector(7 downto 0);

out_mux: out std_logic_vector(7 downto 0));

end mux4;

architecture mux4 of mux4 is

begin

            process(sel_mux)

            begin

                        case sel_mux is

                                    when \"00\" => out_mux<=in0_mux;

                                    when \"01\" => out_mux<=in1_mux;

                                    when \"10\" => out_mux<=in2_mux;

                                    when others => out_mux<=in3_mux;

                        end case;

            end process;

end mux4;

Convert the VHDL Code to Verilog

Solution

module mux4(select,d,q);

intput[1:0] select;

input[3:0] d;

output q;

wire q;

wire[1:0] select;

wire[3:0] d;

assign q=(select==0)?d[0]:(select==1)?d[1]:(select==2)?d[2]:d[3];

endmodule;