Using Quartus 2 software Create one VHDL alu32vhd that has e

Using Quartus 2 software:

Create one VHDL (alu32.vhd) that has exactly the same format as follows.

a, b : in STD_LOGIC_VECTOR(31 downto 0);

ALUControl : in STD_LOGIC_VECTOR(1 downto 0);

Result : buffer STD_LOGIC_VECTOR(31 downto 0);

ALUFlags : out STD_LOGIC_VECTOR(3 downto 0)

);

end alu32;

After running the compiler:

Error (12007): Top-level design entity \"Lab2\" is undefined.

Question: Please explain how to resolve the error and how to get this code to compile.

Solution

Solution: THese are the possible issue that is causoing the error:

1. Make sure that your alu32 is set as the top module in the xilinx software. THis you can do by right click on the file name and select Make the File Top MOdule

2. Now try to compile the code from top menu. You will surely not get any error if your alu32 does not have any syntax error.