Write the VHDL code for 8bit register with asynchronous rese

Write the VHDL code for 8-bit register with asynchronous reset LIBRARY ieee; USE ieee.std_logic_116-4 all; ENTITY rec8 IS PORT(D: IN STD_LOGIC_VECTOR(7 DOWNTO 0); Reset, Clock: IN STD_LOGIC; Q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); END reg8;

Solution

VHDL code for 8-bit register with asynchronous reset is given below,

library IEEE;

use IEEE.std_logic_1164.all;

entity reg8 is

port( D :IN STD_LOGIC_VECTOR(7 DOWNTO 0);

Reset, Clock : IN STD_LOGIC;

Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );

end reg8;

architecture behav of reg8 is

begin

process(Clock,Reset)

begin

if (Reset=’0’) then

Q<=’0’;

elsif (Clock’event and Clock=’1’) then

Q<=D;

end if;

end process;

end behav;