Answer the questions that follow the VHDL code given below W

Answer the questions that follow the VHDL code given below. What do the input variables n_cp and n_rd represent? How many bits are contained in the output q? The code performs a counting function. Is the counter an up counter or a counter or both? What is the MOD number of the counter? Does the counter count on the positive or negative edge of the clock? What VHDL statement can be used to replace: (n_cp \'EVENT AND n_cp^-\'0\')?

Solution

a)

n_cp input represent clock input and n_rd represent asynchronous reset input to the module

b)

0 to 15, means totoal 16 possible outputs are there.so the output must be 4bits wide.

c)its up counter

d)mod-11 counter

e)negative edge

f)negedge(n_cp)