can someone help me with this problem Verilog Implementation

can someone help me with this problem

Verilog Implementation Design of an 8-bit ALU Write the VERILOG code for an 8-bit arithmetic/logic unit (ALU). This should be very reminiscent of the work you did for Lab 2. The ALU has FIVE input vectors. They are: OPCODE: A 4-bit opcode A: An 8-bit vector B: An 8-bit vector RA: A 4-bit vector RB: A 4-bit vector The ALU should operate on the inputs A, B, RA, and RB depending on the control input OPCODE in the following way:

Solution

please find the verilog code as below:

for he first code i am using one more input vector that is enable

when enable high we get the alu_out as the result of the 8 bit alu

if enable is low alu is disable:

please find the code as below with enable input:

module alu(enable,A,B,RA,RB,OPCODE,alu_out);

input enable;
input [7:0] A,B; // 8 bit input vector A,B
input [3:0] RA,RB; // 4 bit input vector RA,RB
output [7:0] alu_out; // 8 bit output port alu_out
input [3:0] OPCODE ; // 4 bit control input vector for ALU
reg [7:0] alu_out; // ALU result vector

always @(*)
begin
if(enable) begin
case ( OPCODE )
4\'b0000: alu_out=8\'Bxxxxxxxx; // alu_out = 8 bit don\'t care
4\'b0001: alu_out={RA,RB} ; // alu_out = concatenation of RA and RB
4\'b0010: alu_out=A+B ; // alu_out = summation of input A and B
4\'b0011: alu_out=A+RB; // alu_out = A + RB
4\'b0100: alu_out=A-B; // alu_out = subtraction of input vector A and B
4\'b0101: alu_out=A|B ; // alu_out = A bitwise or B
4\'b0110: alu_out=A&B; // alu_out = A bitwise and B
4\'b0111: alu_out=A^B; // alu_out = A bitwise xor B
4\'b1000: alu_out=B+1; // alu_out = B+1
4\'b1001: alu_out=B-1; // alu_out = B-1
4\'b1010: alu_out=~B; // alu_out = negation of vector B
4\'b1011: alu_out=8\'bxxxxxxxx; //
4\'b1100: alu_out={RA,RB}; // alu_out = concatenation of RA and RB
default : begin
alu_out=8\'bxxxxxxxx;
$display(\"Illegal opcode detected\");
end
endcase
end

end

endmodule

now fond the code without enable input as we apply the input it gives the result depending upon the OPCODE input:

module alu(enable,A,B,RA,RB,OPCODE,alu_out);

input enable;
input [7:0] A,B; // 8 bit input vector A,B
input [3:0] RA,RB; // 4 bit input vector RA,RB
output [7:0] alu_out; // 8 bit output port alu_out
input [3:0] OPCODE ; // 4 bit control input vector for ALU
reg [7:0] alu_out; // ALU result vector

always @(*)
begin

case ( OPCODE )
4\'b0000: alu_out=8\'Bxxxxxxxx; // alu_out = 8 bit don\'t care
4\'b0001: alu_out={RA,RB} ; // alu_out = concatenation of RA and RB
4\'b0010: alu_out=A+B ; // alu_out = summation of input A and B
4\'b0011: alu_out=A+RB; // alu_out = A + RB
4\'b0100: alu_out=A-B; // alu_out = subtraction of input vector A and B
4\'b0101: alu_out=A|B ; // alu_out = A bitwise or B
4\'b0110: alu_out=A&B; // alu_out = A bitwise and B
4\'b0111: alu_out=A^B; // alu_out = A bitwise xor B
4\'b1000: alu_out=B+1; // alu_out = B+1
4\'b1001: alu_out=B-1; // alu_out = B-1
4\'b1010: alu_out=~B; // alu_out = negation of vector B
4\'b1011: alu_out=8\'bxxxxxxxx; //
4\'b1100: alu_out={RA,RB}; // alu_out = concatenation of RA and RB
default : begin
alu_out=8\'bxxxxxxxx;
$display(\"Illegal opcode detected\");
end
endcase

end

endmodule